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Raji, Mohsen, Ghavami, Behnam, Keshavarzi, Saeed, Mahmoudi, Reza. (1403). GENSO: A Genetic Algorithm-based Optimization Framework for Lifetime Reliability Enhancement in Sequential Circuit Design. نشریه هنرهای کاربردی, 4(4), 41-50. doi: 10.22075/mseee.2025.37658.1212
Mohsen Raji; Behnam Ghavami; Saeed Keshavarzi; Reza Mahmoudi. "GENSO: A Genetic Algorithm-based Optimization Framework for Lifetime Reliability Enhancement in Sequential Circuit Design". نشریه هنرهای کاربردی, 4, 4, 1403, 41-50. doi: 10.22075/mseee.2025.37658.1212
Raji, Mohsen, Ghavami, Behnam, Keshavarzi, Saeed, Mahmoudi, Reza. (1403). 'GENSO: A Genetic Algorithm-based Optimization Framework for Lifetime Reliability Enhancement in Sequential Circuit Design', نشریه هنرهای کاربردی, 4(4), pp. 41-50. doi: 10.22075/mseee.2025.37658.1212
Raji, Mohsen, Ghavami, Behnam, Keshavarzi, Saeed, Mahmoudi, Reza. GENSO: A Genetic Algorithm-based Optimization Framework for Lifetime Reliability Enhancement in Sequential Circuit Design. نشریه هنرهای کاربردی, 1403; 4(4): 41-50. doi: 10.22075/mseee.2025.37658.1212

GENSO: A Genetic Algorithm-based Optimization Framework for Lifetime Reliability Enhancement in Sequential Circuit Design

Modeling and Simulation in Electrical and Electronics Engineering
دوره 4، شماره 4 - شماره پیاپی 18، اسفند 2024، صفحه 41-50    اصل مقاله (829.37 K)
نوع مقاله: Research Paper
شناسه دیجیتال (DOI): 10.22075/mseee.2025.37658.1212
نویسندگان
Mohsen Raji* 1؛ Behnam Ghavami2؛ Saeed Keshavarzi1؛ Reza Mahmoudi1
1School of Electrical and Computer Engineering, Shiraz University, Shiraz, Iran.
2School of Engineering Science at Simon Fraser University, Canada.
تاریخ دریافت: 15 اردیبهشت 1404،  تاریخ بازنگری: 01 تیر 1404،  تاریخ پذیرش: 26 شهریور 1404 
چکیده
Chnology scaling becomes increasingly aggressive, lifetime reliability has emerged as a critical challenge for modern digital circuits, exacerbated by manufacturing process variations and aging effects. This paper introduces GenSO, a Genetic algorithm-based multi-objective Sequential circuit Optimization framework designed to enhance the lifetime reliability of sequential circuits modeled as Finite State Machines (FSMs), while simultaneously addressing initial delay and power consumption. The framework leverages a cross-layer approach, utilizing a gate-level delay degradation model that accounts for process variations and aging to estimate circuit lifetime reliability. A novel metric, termed Guardband-Aware Reliability (GAR), is proposed to provide a fair assessment of FSM lifetime reliability in relation to the guardband and timing yield specified by the designer. A multi-objective genetic algorithm is then employed to optimize delay, power consumption, and lifetime reliability in FSM-based sequential circuits. Experimental results demonstrate that GenSO successfully identifies non-dominated solutions for sequential circuit designs, achieving simultaneous optimization of initial delay, power consumption, and lifetime reliability. With a 15% delay overhead for a 6-year lifetime and a 10% variation ratio, GenSO improves circuit reliability by an average of 64.34%, significantly outperforming state-of-the-art reliability optimization frameworks, which typically achieve less than 30% improvement in lifetime reliability.
کلیدواژه‌ها
Finite State Machines؛ Lifetime Reliability؛ Multi-objective Optimization؛ Process Variations؛ BTI
مراجع
  1. Alam, M.A. and Mahapatra, S., 2005. A comprehensive model of PMOS NBTI degradation. Microelectronics Reliability, 45(1), pp.71-81.
  2. Huard, V., Angot, D. and Cacho, F., 2015, April. From bti variability to product failure rate: A technology scaling perspective. In 2015 IEEE International Reliability Physics Symposium (pp. 6B-3). IEEE.
  3. M. van Santen, J. Martin-Martinez, H. Amrouch, M. M. Nafria and J. Henkel, "Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 293-306, Jan. 2018, doi: 10.1109/TCSI.2017.2717790..
  4. Jafari, A., Raji, M. and Ghavami, B., 2020. Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(12),4761-4773.
  5. Fang, J. and Sapatnekar, S.S., 2013. The impact of BTI variations on timing in digital logic circuits. IEEE Transactions on Device and Materials Reliability, 13(1), pp.277-286.
  6. Diaz-Fortuny, Javier, Mahdi Benkhelifa, Alexander Grill, Erik Bury, Robin Degraeve, Ben Kaczer, and Hussam Amrouch. "Investigation of Cryogenic Aging in 28 nm CMOS: Suppression of BTI and HCD in Circuits and SRAM." In 2025 IEEE International Reliability Physics Symposium (IRPS), pp. 1-7. IEEE, 2025
  7. Sharma, M., Khanna, V., Tonk, A. and Ruhil, S., 2025. Implementation and Comparative Analysis of Various Low Power FSM Synthesis Techniques. Journal of Electronics and Power Engineering (JEPE), vol. 2, no. 1, pp.54-66.
  8. Choudhury M, Gao M, Varna A, Peer E, Forte D. TRANSPOSE: Transitional Approaches for Spatially-Aware LFI Resilient FSM Encoding. arXiv preprint arXiv:2411.02798. 2024 Nov 5.
  9. Babakov, R.M. and Barkalov, A.A., 2025. An Algorithm for Solving the Problem of Algebraic Synthesis of a Finite-State Machine with Datapath of Transitions Based on a Matrix Approach. Cybernetics and Systems Analysis, pp.1-7.
  10. Barkalov, Alexander, Larysa Titarenko, and Kamil Mielcarek. "Transforming Group Codes in Mealy Finite State Machines with Composite State Codes." Applied Sciences 15, no. 8 (2025): 4289.
  11. Al Jassani, B.A., Urquhart, N. and Almaini, A.E.A., 2011. State assignment for sequential circuits using multi-objective genetic algorithm. IET computers & digital techniques, 5(4), pp.296-305.
  12. El-Maleh, A.H., Sheikh, A.T. and Sait, S.M., 2013. Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits. Applied soft computing, 13(12), pp.4832-4840.
  13. El-Maleh, A.H., 2015. Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits. IET Computers & Digital Techniques, 10(1), pp.30-36.
  14. Tao, Y., Zhang, Y. and Wang, Q., 2018. Fuzzy c-mean clustering-based decomposition with GA optimizer for FSM synthesis targeting to low power. Engineering Applications of Artificial Intelligence, 68, pp.40-52.
  15. Tao, Y., Zhang, Y., Wang, Q. and Cao, J., 2018. MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis. IET Computers & Digital Techniques, 12(3), pp.111-120.
  16. Pendyala, S. and Katkoori, S., 2016, March. State encoding based NBTI optimization in finite state machines. In 2016 17th International Symposium on Quality Electronic Design (ISQED) (pp. 416-422). IEEE.
  17. Amrouch, H., van Santen, V.M. and Henkel, J., 2016. Interdependencies of degradation effects and their impact on computing. IEEE Design & Test, 34(3),59-67.
  18. Mukhopadhyay, S., Goel, N. and Mahapatra, S., 2016. A comparative study of NBTI and PBTI using different experimental techniques. IEEE Transactions on Electron Devices, 63(10),4038-4045.
  19. Sexton, R.S., Dorsey, R.E. and Johnson, J.D., 1999. Optimization of neural networks: A comparative analysis of the genetic algorithm and simulated annealing. European Journal of Operational Research, 114(3),589-601.
  20. Zafar, S., Kumar, A., Gusev, E. and Cartier, E., 2005. Threshold voltage instabilities in high-/spl kappa/gate dielectric stacks. IEEE Transactions on Device and Materials Reliability, 5(1),45-64.
  21. Tudor, B., Wang, J., Chen, Z., Tan, R., Liu, W. and Lee, F., 2012. An accurate MOSFET aging model for 28 nm integrated circuit simulation. Microelectronics Reliability, 52(8),1565-1570.
  22. Yang, H.I., Yang, S.C., Hwang, W. and Chuang, C.T., 2011. Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(6),1239-1251.
  23. Wenping Wang, Zile Wei, Shengqi Yang and Yu Cao, "An efficient method to identify critical gates under circuit aging," 2007 IEEE/ACM International Conference on Computer-Aided Design, 2007, pp. 735-740, doi: 10.1109/ICCAD.2007.4397353
  24. Gomez, and V.Champac, “An efficient metric-guided gate sizing methodology for guardband reduction under process variations and aging effects,” Journal of Electronic Testing, vol. 35, No. 1, pp. 87-100, 2019.
  25. Raji, M., Mahmoudi, R., Ghavami, B. and Keshavarzi, S., 2021. Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment. IEEE Access, 9, pp.114120-114134.
  26. Wang, W., Reddy, V., Yang, B., Balakrishnan, V., Krishnan, S. and Cao, Y., 2008, September. Statistical prediction of circuit aging under process variations. In 2008 IEEE Custom Integrated Circuits Conference(pp. 13-16). IEEE.
  27. Blaauw, D., Chopra, K., Srivastava, A. and Scheffer, L., 2008. Statistical timing analysis: From basic principles to state of the art. IEEE transactions on computer-aided design of integrated circuits and systems, 27(4),589-607.
  28. Papoulis, A. and Pillai, S.U., 2002. Probability, random variables, and stochastic processes. Tata McGraw-Hill Education.
  29. Goldberg, D.E., 1989. Genetic algorithms in search, optimization, and machine learning. Reading.
  30. http://www.pld.ttu.ee/applets/dsa/Libs/sis/
  31. https://people.eecs.berkeley.edu/~alanmi/abc/
  32. http://ptm.asu.edu/
  33. Agarwal, A., Blaauw, D. and Zolotov, V., 2003, November. Statistical timing analysis for intra-die process variations with spatial correlations. In ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No. 03CH37486)(pp. 900-907). IEEE.
  34. Pendyala, S. and Katkoori, S., 2016, March. State encoding based NBTI optimization in finite state machines. In 2016 17th International Symposium on Quality Electronic Design (ISQED)(pp. 416-422). IEEE.
  35. Zizheng Guo, Tsung-Wei Huang, and Yibo Lin. 2020. GPU-accelerated static timing analysis. In Proceedings of the 39th International Conference on Computer-Aided Design (ICCAD '20), 2020, pp. 1–9.
  36. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, “Estimate of signal probability in combinational logic networks,” in [1989] Proceedings of the 1st European Test Conference, 1989, pp. 132–138.
  37. Davidson, “ITC’99 benchmark circuits-preliminary results,” in International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034), pp. 1125–1125, IEEE, 1999.
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