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طراحی ترانزیستور اثر میدانی تونلی بدون پیوند ناهمگن همراه شده با فناوری Silicon-on-Nothing برای بهبود مشخصات DC | ||
| مدل سازی در مهندسی | ||
| دوره 22، شماره 76، اردیبهشت 1403، صفحه 45-53 اصل مقاله (1.28 M) | ||
| نوع مقاله: مقاله پژوهشی | ||
| شناسه دیجیتال (DOI): 10.22075/jme.2023.29572.2392 | ||
| نویسندگان | ||
| امین ونک1؛ امیر امینی* 2 | ||
| 1دانشجوی دکتری دانشکده مهندسی برق، دانشگاه آزاد اسلامی تهران غرب، تهران، ایران | ||
| 2دانشیار دانشکده مهندسی برق، دانشگاه آزاد اسلامی تهران غرب، تهران، ایران | ||
| تاریخ دریافت: 21 دی 1401، تاریخ بازنگری: 27 تیر 1402، تاریخ پذیرش: 12 شهریور 1402 | ||
| چکیده | ||
| دراین مقاله، ترانزیستور اثر میدانی تونلی بدون پیوند ناهمگن همراه شده با تکنولوژی silicon-on-nothing (SON HS-JLTFET) پیشنهاد می‌شود. ترانزیستور پیشنهادی در مقایسه با ترانزیستور تونل‌زنی بدون پیوند مرسوم دو مزیت دارد. اولین مزیت، یک دهه افزایش در جریان روشنی و بهبود 10 درصدی نوسانات زیر آستانه است که بخاطر استفاده از InAs در ناحیه‌ی سورس می‌باشد. InAs به دلیل انرژی شکاف باند کمتری که نسبت به Si دارد سبب پهنای سد تونل‌زنی کمتر در پیوند سورس/کانال می‌شود. لذا الکترون های بیشتری از سورس به کانال تونل زنی میکنند. در نتیجه سبب افزایش نرخ تونل‌زنی و بهبود در جریان روشنی و نوسان زیر آستانه می‌شود. مزیت دیگر شامل کاهش جریان ambipolar به کمک تکنیک SON است. در واقع، air به دلیل ثابت دی الکتریک کمتری که نسبت به اکسید SiO2 دارد میدان الکتریکی را در پیوند درین/کانال کاهش می‌دهد.میدان کاهش یافته سبب پهنای سد بزرگتری می‌شود. لذا جریان ambipolar را کاهش می‌دهد. | ||
| کلیدواژه‌ها | ||
| ترانزیستور تونل‌زنی؛ نوسانات زیر آستانه؛ جریان ambipolar؛ ساختار ناهمگن | ||
| عنوان مقاله [English] | ||
| A New Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-Nothing Technique for DC Parameter Improvement | ||
| نویسندگان [English] | ||
| Amin Vanak1؛ Amir Amini2 | ||
| 1Doctoral student, Department of Electrical Engineering, College of Technical and Engineering, West Tehran Branch, Islamic Azad University, Tehran, Iran. | ||
| 2Associate Professor, Department of Electrical Engineering, College of Technical and Engineering, West Tehran Branch, Islamic Azad University, Tehran, Iran. | ||
| چکیده [English] | ||
| In this paper, a novel heterostructure junctionless tunnel field effect transistor with silicon-on-nothing technology (SON HS-JLTFET) is proposed. The proposed device has two advantages over conventional JLTFET. First, one decade of increment in the ON current is achieved and subthreshold swing is improved by 10%. In this device, InAs is used in the source region of SON HS-JLTFET which has a lower energy band gap than Si to achieve thinner tunneling barrier width. Hence, more electron can tunnel from source to channel. As a result, it provides improvements in drain current and subthreshold swing. The second advantage is that the ambipolar current reduction due to the use of SON technique. In fact, in this technique, air is considered as the gate dielectric which results in decrement in the electric field in the drain/channel junction. This reduced electric field causes increasing the width of the tunneling barrier which results in lower ambipolar current in the drain/channel junction. . | ||
| کلیدواژه‌ها [English] | ||
| Tunnel field effect, Transistor, Subthreshold swing, Ambipolar current, Heterostructure | ||
| مراجع | ||
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[1] B. Abdi Tahneh, , and A. Naderi. "A new tunneling carbon nanotube field effect transistor with linear doping profile at drain region: numerical simulation study." Journal of Modeling in Engineering 16, no. 52 (2018): 109-117. (in Persian) [2] A.A. Orouji, A. Anbarheydari, and Z. Ramezani. "4H-SiC MESFET with darin-side and undoped region for modifying charge distribution and high power applications." Journal of Modeling in Engineering 13, no. 43 (2015): 121-127. (in Persian) [3] K. Boucart, and A.M. Ionescu. "Double-gate tunnel FET with high-$\kappa $ gate dielectric." IEEE Transactions on Electron Devices 54, no. 7 (2007): 1725-1733. [4] A.M. Ionescu, and H. Riel. "Tunnel field-effect transistors as energy-efficient electronic switches." Nature 479, no. 7373 (2011): 329-337. [5] J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'neill, A. Blake, M. White, and A.M. Kelleher. "Nanowire transistors without junctions." Nature Nanotechnology 5, no. 3 (2010): 225-229. [6] H. Aghandeh, and S.A. Sedigh Ziabari. "Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement." Superlattices and Microstructures 111 (2017): 103-114. [7] B.V. Chandan, M. Gautami, K. Nigam, D. Sharma, V.A. Tikkiwal, S. Yadav, and S. Kumar. "Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance." Journal of Computational Electronics 18 (2019): 76-82. [8] S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan. "On enhanced Miller capacitance effect in interband tunnel transistors." IEEE Electron Device Letters 30, no. 10 (2009): 1102-1104. [9] W.V. Devi, and B. Bhowmick. "Optimisation of pocket doped junctionless TFET and its application in digital inverter." Micro & Nano Letters 14, no. 1 (2019): 69-73. [10] M. Vadizadeh. "Digital performance assessment of the dual-material gate GaAs/InAs/Ge junctionless TFET." IEEE Transactions on Electron Devices 68, no. 4 (2021): 1986-1991. [11] V.P.H. Hu, and C.T. Wang. "Optimization of III–V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression." Japanese Journal of Applied Physics 57, no. 4S (2018): 04FD18. [12] B.V. Chandan, K. Nigam, S. Tirkey, and D. Sharma. "Metal-strip approach on junctionless TFET in the presence of positive charge." Applied Physics A 125 (2019): 1-12. [13] S.Tirkey, D. Sharma, D.S. Yadav, and S. Yadav. "Analysis of a novel metal implant junctionless tunnel FET for better DC and analog/RF electrostatic parameters." IEEE Transactions on Electron Devices 64, no. 9 (2017): 3943-3950. [14] A. Mahajan, D.K. Dash, P. Banerjee, and S.K. Sarkar. "Analytical modeling of triple-metal hetero-dielectric DG SON TFET." Journal of Materials Engineering and Performance 27 (2018): 2693-2700. [15] A. Kaity, S. Singh, and P.N. Kondekar. "Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (SON-ED-JLTFET): A short channel effect resilient design." Silicon 13 (2021): 9-23. [16] Bu W.H, H. Ru, L. Ming, T. Yu, W. Da-Ke, C. Man-Sun, and W. Yang-Yuan. "Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation." Chinese Physics 15, no. 11 (2006): 2751. [17] J. Pretet, S. Monfray, S. Cristoloveanu, and T. Skotnicki. "Silicon-on-nothing MOSFETs: performance, short-channel effects, and backgate coupling." IEEE Transactions on Electron Devices 51, no. 2 (2004): 240-245. [18] K. Eyvazi, and M.A. Karami. "Suppressing ambipolar current in UTFET by auxiliary gate." Iranian Journal of Science and Technology, Transactions of Electrical Engineering 45 (2021): 407-414. [19] A. Naderi, and M. Ghodrati. "Improvement in the Performance of Tunneling Carbon Nanotube Field Effects Transistor in Presence of Underlap." Journal of Modeling in Engineering 17, no. 59 (2019): 215-224. (in Persian) [20] B. Ghosh, and M.W. Akram. "Junctionless tunnel field effect transistor." IEEE Electron Device Letters 34, no. 5 (2013): 584-586. [21] K. Eyvazi, and M.A. Karami. "Analytical modeling and simulation of a triple-material double-gate SON TFET with stacked front-gate oxide for low-power applications." Iranian Journal of Science and Technology, Transactions of Electrical Engineering 47, no. 3 (2023): 845-858. [22] W.V. Devi, and B. Bhowmick. "Optimisation of pocket doped junctionless TFET and its application in digital inverter." Micro & Nano Letters 14, no. 1 (2019): 69-73. [23] F. Khorramrouze, S.A. Sedigh Ziabari, and A. Heydari. "Design and Realization of a Junction-less TFET for Analog and Digital Applications Based on Strain Engineering." Majlesi Journal of Telecommunication Devices 11, no. 2 (2022): 66-74. [24] A.Vanak, A. Amini, and S.H. Pishgar. "Improvements in reliability and rf performance of stacked gate jltfet using p+ pocket and heterostructure material." Silicon 15, no. 9 (2023): 4137-4147.
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