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کاهش مؤلفه ناخواسته مرجع در فرکانس سازهای عدد صحیح | ||
| مدل سازی در مهندسی | ||
| دوره 23، شماره ویژه 81، تیر 1404، صفحه 199-207 اصل مقاله (925.11 K) | ||
| نوع مقاله: مقاله پژوهشی | ||
| شناسه دیجیتال (DOI): 10.22075/jme.2024.31082.2481 | ||
| نویسندگان | ||
| سکینه جهانگیرزاده* ؛ عاطفه رحیمی فر | ||
| گروه برق، مؤسسه آموزش عالی کارون، اهواز، ایران | ||
| تاریخ دریافت: 14 تیر 1402، تاریخ بازنگری: 13 مرداد 1403، تاریخ پذیرش: 01 مهر 1403 | ||
| چکیده | ||
| فرکانس‌ساز نقش مهمی را در فرستنده وگیرنده‌های RF ایفا میکند. غیرایده‌آل بودن مدار تلمبه‌ی بار و آشکارساز فاز- فرکانس مؤلفه‌های ناخواسته‌ای در خروجی فرکانس‌ساز ایجاد میکند. در این مقاله یک روش جدید برای کاهش مؤلفه ناخواسته مرجع در فرکانس‌ساز پیشنهاد شده است. سیستم کاهش مؤلفه ناخواسته مرجع بین تلمبه‌ی بار و فیلتر پایین گذر به‌منظور کاهش دامنه ریپل‌های متناوب روی ولتاژ کنترل، اسیلاتور کنترل شده ولتاژ (VCO) قرار گرفته است. توسط کاهش دادن دامنه ریپل‌های متناوب، مؤلفه ناخواسته مرجع تضعیف می‌شود. ساختار پیشنهادی نیاز برای کاهش پهنای‌باند و کاهش گین VCO برای سرکوب مؤلفه ناخواسته مرجع را حذف میکند. برای نشان دادن اثرات ساختار پیشنهادی یک مولد فرکانسی GHz 22/2- 06/2 و کلاک مرجع MHz20 طراحی شده است و شبیه‌سازی post-layout با استفاده از فناوری180 نانومتر CMOSانجام شده است. سطح مؤلفه ناخواسته مرجع در فاصله 20 MHz مقدارش dBc84/85- و در فاصله 200 KHz مقدار نویز فاز dBc/Hz108- بدست آمده است و زمان قفل ساختار پیشنهادی حدود 3 /2 بدست آمده است. | ||
| کلیدواژه‌ها | ||
| مولد فرکانسی عدد صحیح؛ مؤلفه ناخواسته مرجع؛ اسیلاتور کنترل شده ولتاژ(VCO) | ||
| عنوان مقاله [English] | ||
| Reduction of Reference Spur in the Integer-N Frequency Synthesizers | ||
| نویسندگان [English] | ||
| Sakineh Jahangirzadeh؛ Atefeh Rahimifar | ||
| Department of Electrical Engineering, Karoon Higher Education Institute, Ahvaz, Iran | ||
| چکیده [English] | ||
| The frequency generator plays an important role in RF transmitters and receivers. The non-ideality of the circuit of the charge pump and the phase-frequency detector creates spurious tones in the Frequency synthesizer output. In this paper, a new technique is proposed to reduce the reference spur in frequency synthesizer. A spur reduction system is inserted between the charge pump and the low pass filter to reduce the amplitude of periodic ripples on the VCO control voltage. By lowering the amplitude of the periodic ripple on the VCO control voltage, we managed to lower the reference spur. The introduced technique removes the necessity to decrease bandwidth and VCO gain reference spur suppressing. To demonstrate the effectiveness of the proposed structure, a 2.06 – 2.22 GHz frequency synthesizer was used and the 180-nm CMOS technology was used for post-layout simulation. The proposed frequency synthesizer represents the reference spur of -85.84 dBc at 20 MHz offset and phase noise of -108dBc/Hz at 200 kHz offset frequency also it is locked after 2.3us. | ||
| کلیدواژه‌ها [English] | ||
| Integer-N frequency synthesize, Reference spur, Voltage controlled oscillator (VCO) | ||
| مراجع | ||
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