Reduction of Reference Spur in the Integer-N Frequency Synthesizers | ||
| مدل سازی در مهندسی | ||
| Volume 23, Special Issue 81, July 2025, Pages 199-207 PDF (925.11 K) | ||
| Document Type: Research Paper | ||
| DOI: 10.22075/jme.2024.31082.2481 | ||
| Authors | ||
| Sakineh Jahangirzadeh* ; Atefeh Rahimifar | ||
| Department of Electrical Engineering, Karoon Higher Education Institute, Ahvaz, Iran | ||
| Receive Date: 05 July 2023, Revise Date: 03 August 2024, Accept Date: 22 September 2024 | ||
| Abstract | ||
| The frequency generator plays an important role in RF transmitters and receivers. The non-ideality of the circuit of the charge pump and the phase-frequency detector creates spurious tones in the Frequency synthesizer output. In this paper, a new technique is proposed to reduce the reference spur in frequency synthesizer. A spur reduction system is inserted between the charge pump and the low pass filter to reduce the amplitude of periodic ripples on the VCO control voltage. By lowering the amplitude of the periodic ripple on the VCO control voltage, we managed to lower the reference spur. The introduced technique removes the necessity to decrease bandwidth and VCO gain reference spur suppressing. To demonstrate the effectiveness of the proposed structure, a 2.06 – 2.22 GHz frequency synthesizer was used and the 180-nm CMOS technology was used for post-layout simulation. The proposed frequency synthesizer represents the reference spur of -85.84 dBc at 20 MHz offset and phase noise of -108dBc/Hz at 200 kHz offset frequency also it is locked after 2.3us. | ||
| Keywords | ||
| Integer-N frequency synthesize; Reference spur; Voltage controlled oscillator (VCO) | ||
| References | ||
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