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بهبود عملکرد ترانزیستور تونل زنی عمودی مبتنی بر ژرمانیوم با به‌کارگیری GaAs به عنوان کانال | ||
| مدل سازی در مهندسی | ||
| دوره 22، شماره 76، اردیبهشت 1403، صفحه 115-122 اصل مقاله (1.16 M) | ||
| نوع مقاله: مقاله پژوهشی | ||
| شناسه دیجیتال (DOI): 10.22075/jme.2023.26379.2231 | ||
| نویسندگان | ||
| شعیب بابایی توسکی1؛ محمد جواد رضایی2؛ سید منوچهر حسینی* 3 | ||
| 1استادیار، دانشکده مهندسی برق، دانشگاه صنعتی همدان، همدان، ایران | ||
| 2دانشجو، دانشکده مهندسی برق، دانشگاه صنعتی همدان، همدان، ایران | ||
| 3استاد، دانشکده مهندسی برق، دانشگاه بوعلی سینا، همدان، ایران | ||
| تاریخ دریافت: 13 اسفند 1400، تاریخ بازنگری: 14 فروردین 1402، تاریخ پذیرش: 09 مهر 1402 | ||
| چکیده | ||
| در این مقاله ترانزیستور تونلزنی عمودی مبتنی بر ژرمانیوم بررسی شدهاست. ویژگیهای الکتریکی ترانزیستور در دو حالت استفاده از ژرمانیوم و همچنین استفاده از گالیوم-آرسناید به عنوان کانال مقایسه شده و شبیه‌سازی آن توسط نرم‌افزار سیلواکو و با استفاده از مدل تونلزنی غیر محلی انجام شدهاست. نتایج نشان می‌دهد که جریان روشنایی بیشتر، جریان خاموشی کمتر و جریان دوقطبی درین کمتر در ولتاژ گیت منفی از مزایای استفاده از گالیوم-آرسناید به جای ژرمانیوم به عنوان کانال است. در ادامه، پارامترهای کانال تغییر داده شده‌اند و اثر تغییر آن‌ها بر روی رفتار ترانزیستور مطالعه شدهاست. افزایش طول کانال باعث کاهش جریان خاموشی و افزایش نسبت جریان روشنایی به خاموشی شده و همچنین باعث کاهش شیب زیرآستانه میشود. از طرف دیگر، افزایش عرض کانال، باعث کاهش نسبت جریان روشنایی به خاموشی و افزایش شیب زیرآستانه میشود. نسبت جریان روشنایی به خاموشی با افزایش طول کانال و کاهش عرض کانال افزایش مییابد و این نسبت میتواند تا 15+10×5/1 افزایش پیدا کند. | ||
| کلیدواژه‌ها | ||
| ترانزیستور عمودی؛ تونل زنی؛ سیلواکو؛ ژرمانیوم؛ گالیوم-آرسناید؛ جریان روشنایی؛ جریان خاموشی | ||
| عنوان مقاله [English] | ||
| Improving Performance of Germanium-Based Vertical Tunneling Field Effect Transistor Using GaAs as Channel | ||
| نویسندگان [English] | ||
| Shoaib Babaei tooski1؛ Mohammad Javad Rezaei2؛ Seyed Manoochehr Hoseini3 | ||
| 1Assistant Professor, Department of Electrical Engineering, Hamedan University of Technology, Hamedan, Iran | ||
| 2MSc, Department of Electrical Engineering, Hamedan University of Technology, Hamedan, Iran | ||
| 3Professor, Department of Electrical Engineering, Bu-Ali Sina University, Hamedan, Iran | ||
| چکیده [English] | ||
| In this paper, Germanium-based vertical tunneling transistors are investigated and the electrical properties of the transistor in two modes of Germanium utilization as well as Gallium Arsenide as the channel are compared. The simulation of this transistor was performed by Silvaco software using non-local tunneling model. The results show that more ON-current, less OFF-current and less bipolar current at negative gate voltage are the advantages of using Gallium Arsenide instead of Germanium as the channel. In the following, the channel parameters are changed and the effect of their change on the behavior of the transistor is studied. Increasing the channel length reduces the Off-current and increases the On-current to Off-current ratio, as well as reducing the sub-threshold slope. On the other hand, increasing the channel width reduces On-current to Off-current ratio and increases the sub-threshold slope. The On-current to Off-current ratio increases with increasing channel length and decreasing channel width, and increases to 1.5 × 10 + 15. . | ||
| کلیدواژه‌ها [English] | ||
| Vertical transistor, Tunneling, Silvaco, Germanium, Gallium arsenide, On-current, Off-Current | ||
| مراجع | ||
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[1] R.H. Yan, A. Ourmazd, and K.F. Lee. "Scaling the Si MOSFET: From bulk to SOI to bulk." IEEE Transactions on Electron Devices 39, no. 7 (1992): 1704-1710. [2] K. Nakamura, N. Nagamura, K. Ueno, T. Taniguchi, K. Watanabe, and K. Nagashio. "All 2D heterostructure tunnel field-effect transistors: impact of band alignment and heterointerface quality." ACS Applied Materials & Interfaces 12, no. 46 (2020): 51598-51606. [3] F. Najam, and Y.S. Yu. "Impact of quantum confinement on band-to-band tunneling of line-tunneling type L-shaped tunnel field-effect transistor." IEEE Transactions on Electron Devices 66, no. 4 (2019): 2010-2016. [4] I. Gayduchenko, S.G. Xu, G. Alymov, M. Moskotin, I. Tretyakov, T. Taniguchi, K. Watanabe, G. Goltsman, A.K. Geim, G. Fedorov, and D. Svintsov. "Tunnel field-effect transistors for sensitive terahertz detection." Nature Communications 12, no. 1 (2021): 543. [5] C.S. Pang, S.J. Han, and Z. Chen. "Steep slope carbon nanotube tunneling field-effect transistor." Carbon 180 (2021): 237-243. [6] B. Abdi Tahneh, and A. Naderi. "A new tunneling carbon nanotube field effect transistor with linear doping profile at drain region: numerical simulation study." Journal of Modeling in Engineering 16, no. 52 (2018): 109-117. (in Persian) [7] A. Naderi, and M. Ghodrati. "Improvement in the Performance of Tunneling Carbon Nanotube Field Effects Transistor in Presence of Underlap." Journal of Modeling in Engineering 17, no. 59 (2019): 215-224. (in Persian) [8] A.A. Orouji, A. Anbarheydari, and Z. Ramezani. "4H-SiC MESFET with darin-side and undoped region for modifying charge distribution and high power applications." Journal of Modeling in Engineering 13, no. 43 (2015): 121-127. (in Persian) [9] S.S. Afzali, A.A. Orouji, and Z. Ramezani. "Triple-Gate MOSFET Transistor using the Silicon-Germanium Tunneling Diode for Kink Effect Improvement." Tabriz Journal of Electrical Engineering 48, no. 3 (2018): 985-990. (in Persian) [10] N. Bashiri, and R. Hosseini. "Design and Analysis of a Multi Material Double Gate Junctionless Tunnel Field Effect Transistor." Journal of Iranian Association of Electrical and Electronics Engineers 18, no. 4 (2021): 71-77. (in Persian) [11] S.M. Sajjadi, and S. Mohammadi. "Effects of Energy Band Gap Traps on Drain Current in Tunneling Field Effect Transistors." Tabriz Journal of Electrical Engineering 50, no. 4 (2021): 1639-1645. (inPersian) [12] S. Kim, G. Myeong, W. Shin, H. Lim, B. Kim, Ta. Jin, S. Chang, K. Watanabe, T. Taniguchi, and S. Cho. "Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches." Nature Nanotechnology 15, no. 3 (2020): 203-206. [13] A.C. Seabaugh, and Q. Zhang. "Low-voltage tunnel transistors for beyond CMOS logic." Proceedings of the IEEE 98, no. 12 (2010): 2095-2110. [14] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat. "Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and≪ 60mV/dec subthreshold slope." In 2008 IEEE International Electron Devices Meeting, pp. 1-3. IEEE, 2008. [15] P.F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch. "Complementary tunneling transistor for low power application." Solid-State Electronics 48, no. 12 (2004): 2281-2286. [16] K. Boucart, and A.M. Ionescu. "Double-gate tunnel FET with high-$\kappa $ gate dielectric." IEEE Transactions on Electron Devices 54, no. 7 (2007): 1725-1733. [17] K.K Bhuwalka, J. Schulze, and I. Eisele. "A simulation approach to optimize the electrical parameters of a vertical tunnel FET." IEEE Transactions on Electron Devices 52, no. 7 (2005): 1541-1547. [18] A.S.Verhulst, W.G. Vandenberghe, K. Maex, S. De Gendt, M.M. Heyns, and G. Groeseneken. "Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates." IEEE electron device letters 29, no. 12 (2008): 1398-1401. [19] T. Krishnamohan, D. Kim, C.D. Nguyen, C. Jungemann, Y. Nishi, and K.C. Saraswat. "High-mobility low band-to-band-tunneling strained-germanium double-gate heterostructure FETs: Simulations." IEEE Transactions on Electron Devices 53, no. 5 (2006): 1000-1009. [20] S. Singh, and B. Raj. "Analytical and compact modeling analysis of a SiGe hetero-material vertical L-shaped TFET." Silicon 14, no. 5 (2022): 2135-2145. [21] J. Yu, S. Kim, D. Ryu, K. Lee, C. Kim, J.H. Lee, S. Kim, and B.G. Park. "Investigation on ambipolar current suppression using a stacked gate in an L-shaped tunnel field-effect transistor." Micromachines 10, no. 11 (2019): 753. [22] D.B. Abdi, and M. Jagadesh Kumar. "Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain." IEEE Journal of the Electron Devices Society 2, no. 6 (2014): 187-190. [23] S. Kumar, K.S. Singh, K. Nigam, and S. Chaturvedi. "Ambipolarity suppressed dual-material double-source T-shaped tunnel field-effect transistor." Silicon 13 (2021): 2065-2070. [24] J.S. Kim, Y.J. Yoon, J.H. Seo, Y.I. Jang, J.H. Lee, S. Cho, G.M. Yoo, and I.M. Kang. "High-performance Ge/GaAs heterojunction tunneling FET with a channel engineering for sub-0.5 V operation." Semiconductor Science and Technology 30, no. 3 (2015): 035020. [25] C. Rajan, D. Sharma, and D.P. Samajdar. "Implementation of physical unclonable functions using hetero junction based GAA TFET." Superlattices and Microstructures 126 (2019): 72-82. [26] R. Juyal, and S.S. Chauhan. "TCAD simulation of Ge-GaAs hetrojunction dopingless tunnel field effect transistor." In 2016 International Conference on Communication and Signal Processing (ICCSP), pp. 1434-1437. IEEE, 2016. [27] B.C. Mech, K. Koley, and J. Kumar. "Ge–GaAs–Ge heterojunction MOSFETs for mixed-signal applications." IEEE Transactions on Electron Devices 67, no. 9 (2020): 3585-3591. [28] M.F. Jawad, T. Rahman, and J.K. Saha. "Performance enhancement of ge/gaas heterostructure tunnelling field effect transistor." In 2020 IEEE 10th International Conference Nanomaterials: Applications & Properties (NAP), pp. 01TPNS02-1. IEEE, 2020.. [29] Y.J. Yoon, J.H. Seo, S. Cho, H.I. Kwon, J.H. Lee, and I.M. Kang. "Sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor with vertical tunneling operation for ultra-low-power applications." JSTS: Journal of Semiconductor Technology and Science 16, no. 2 (2016): 172-178. | ||
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